library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; entity FIFO is Port ( CLK : in STD_LOGIC; Schreiben: in STD_LOGIC; Lesen : in STD_LOGIC; Data_in : in STD_LOGIC_VECTOR (39 downto 0); Data_out : out STD_LOGIC_VECTOR (39 downto 0); Start : out STD_LOGIC); end FIFO; architecture Verhalten of FIFO is signal Schreibadresse, Leseadresse : unsigned (9 downto 0) := (others => '0'); type speicher is array(0 to 1023) of std_logic_vector(39 downto 0); signal memory : speicher; begin process begin wait until rising_edge(CLK); if Schreiben = '1' then memory(to_integer(Schreibadresse)) <= Data_in; Schreibadresse <= Schreibadresse + 1; end if; if Lesen = '1' then Data_out <= memory(to_integer(Leseadresse)); Leseadresse <= Leseadresse + 1; Start <= '1'; else Start <= '0'; end if; end process; end Verhalten;